1. Field of the Invention
The present invention relates to MOS transistors and, more particularly, to a multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions.
2. Description of the Related Art
A MOS transistor is a well-known semiconductor device that can be fabricated in many well known ways. MOS transistors can be formed as n-channel (NMOS) devices or as p-channel (PMOS) devices. In addition, MOS transistors can be formed as low-voltage devices or as high-voltage devices.
FIGS. 1A and 1B show views that illustrate a prior-art, single-source, single-gate, high-voltage PMOS transistor 100. FIG. 1A shows a schematic layout that represents a plan view of transistor 100, while FIG. 1B shows a cross-sectional view of transistor 100 taken along line 1B—1B of FIG. 1A.
As shown in FIGS. 1A and 1B, PMOS transistor 100 includes an n-type semiconductor material 110, and spaced-apart p-type source and drain regions 112 and 114 that are formed in semiconductor material 110. Source region 112 includes a heavily-doped (p+) region, while drain region 114 includes an extended lightly-doped (p−) region 114A and a heavily-doped (p+) region 114B.
PMOS transistor 100 also includes a channel region 116 of semiconductor material 110 that lies between the source and drain regions 112 and 114, and a layer of insulation material 120, such as gate oxide, that lies over channel region 116. Further, transistor 100 includes a gate 122, such as polysilicon, that lies on insulation material 120 over channel region 116.
In addition, PMOS transistor 100 includes an isolation material ISO that surrounds transistor 100. Isolation material ISO lies adjacent to the two short sides, and the long side of p+ drain region 114B. P+ drain region 114B must be formed a distance WC from the nearest edge of isolation material ISO. On the other hand, isolation material ISO contacts source region 112, extended p− region 114A, and channel region 116.
In operation, when a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, PMOS transistor 100 turns on and holes flow from source region 112 to drain region 114. When the gate-to-source voltage VGS is more positive than the threshold voltage, PMOS transistor 100 turns off and no holes (other than a very small leakage current) flow from source region 112 to drain region 114.
FIGS. 2A and 2B show views that illustrate a prior-art, dual-source, dual-gate, high-voltage PMOS transistor 200. FIG. 2A shows a schematic layout that represents a plan view of transistor 200, while FIG. 2B shows a cross-sectional view of transistor 200 taken along line 2B—2B of FIG. 2A.
As shown in FIGS. 2A and 2B, PMOS transistor 200 includes an n-type semiconductor material 210, spaced-apart p-type source regions 212A and 212B that are formed in semiconductor material 210, and a drain region 214 that is formed in semiconductor material 210 between, and spaced apart from, the source regions 212A and 212B.
Source regions 212A and 212B have heavily-doped (p+) regions. On the other hand, drain region 214 includes an extended lightly-doped (p−) region 214A, and a heavily-doped (p+) region 214B that is surrounded at the surface by p− region 214A. Drain region 214 always receives holes when transistor 200 is turned on, while source regions 212A and 212B always provide holes when transistor 200 is turned on. In addition, source regions 212A and 212B have a width W1 that is greater than a width W2 of p+ drain region 214B.
PMOS transistor 200 also includes a first channel region 216A of semiconductor material 210 that lies between the source and drain regions 212A and 214A, and a second channel region 216B of semiconductor material 210 that lies between the source and drain regions 212B and 214A.
In addition, PMOS transistor 200 includes an isolation material ISO that surrounds transistor 200. Isolation material ISO contacts the source regions 212A and 212B, the extended p− region 214A, and the first and second channel regions 216A and 216B. Further, both the top and bottom sides of p+ drain region 214B must be formed a width WC from the nearest edge of isolation material ISO. As a result, the width W2 of p+ drain region 214B is 2 WC less than the width W1 of p+ source and drain regions 212A and 212B.
PMOS transistor 200 additionally includes a first insulation layer 220A, such as gate oxide, that lies over channel region 216A, and a second insulation layer 220B, such as gate oxide, that lies over channel region 216B. PMOS transistor 200 further includes a first gate 222A, such as polysilicon, that lies on insulation layer 220A over channel region 216A, and a second gate 222B, such as polysilicon, that lies on insulation layer 220B over channel region 216B.
In operation, when source regions 212A and 212B are electrically connected together, gates 222A and 222B are electrically connected together, a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, PMOS transistor 200 turns on and holes flow from both of the source regions 212A and 212B to drain region 214.
When the gate-to-source voltage VGS is more positive than the threshold voltage, PMOS transistor 200 turns off and no holes (other than a very small leakage current) flow from the source regions 212A and 212B to drain region 214. Due to the multi-fingered structure, PMOS transistor 200 sources more current than PMOS transistor 100.
PMOS transistors 100 and 200 are both in common use, with transistor 200 often being preferred over transistor 100 because of the greater current capacity and reduced effective area of transistor 200. One problem with transistor 200, however, is that transistor 200 has an accelerated drain breakdown voltage walk-in.
When PMOS transistor 200 is initially fabricated, transistor 200 has a drain-to-semiconductor material breakdown voltage. Over time, however, positive hot charge carriers become trapped at the silicon—silicon dioxide interface (between semiconductor material 210 and insulation layers 220A and 220B) near drain region 214 which, in turn, causes the drain breakdown voltage to change.
When the trapped charge carriers cause the drain breakdown voltage of a PMOS transistor to decrease over time, the process is known as drain breakdown voltage walk-in. (Walk-out can also occur.) Continued drain breakdown voltage walk-in eventually leads to the failure of the device. As a result, a device that has an accelerated drain breakdown voltage walk-in is a device that can fail prematurely due to changes in the drain breakdown voltage.
FIG. 3 shows a graph that illustrates the drain breakdown voltage walk-ins of five prior-art, high-voltage PMOS transistors when stressed for varying periods of time. In this example, the stress times and temperature are VGS=−14V, VDS=−100V, and Temp=110° C. When the drain breakdown voltage has walked-in by 30V, the device is considered to have failed.
The five high-voltage PMOS transistors include a (100/3.5) double gate (combined) transistor 310, a (100/3.5) double gate (separated) transistor 312 (which represents transistor 200), a (50/3.5) double gate (combined) transistor 314, a (100/3.5) single gate transistor 316 (which represents transistor 100), and a (50/3.5) single gate transistor 318.
As shown in FIG. 3, the drain breakdown voltage of PMOS transistor 316 (which represents PMOS transistor 100) remains unchanged when stressed up to 100 kS. After this, however, the drain breakdown voltage walks in quickly and exceeds the 30V failure point. On the other hand, the drain breakdown voltage of PMOS transistor 312 (which represents PMOS transistor 200) remains unchanged for only 100 s. After 300 s, the drain breakdown voltage also walks in quickly and exceeds the 30V failure point.
Thus, as shown in FIG. 3, dual-source, dual-gate, high-voltage PMOS transistor 312 (which represents transistor 200) has a drain breakdown voltage that walks-in approximately 500× faster than the drain breakdown voltage of single-source, single-gate, high-voltage PMOS transistor 318 (which represents transistor 100). As a result, there is a need for a high-voltage, multi-gate PMOS transistor that has a reduced drain breakdown voltage walk-in rate.